Accurate and Extensible Symbolic Execution of Binary Code based on Formal ISA Semantics.
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Poster
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2025.
Accurate Binary-Level Symbolic Execution of Embedded Firmware.
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Staats- und Universitätsbibliothek Bremen (SUUB), 2024.
Minimally Invasive Generation of RISC-V Instruction Set Simulators from Formal ISA Models.
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DOI
Forum for Specification and Design Languages (FDL), 2023.
Versatile and Flexible Modelling of the RISC-V Instruction Set Architecture.
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DOI
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24th International Symposium on Trends in Functional Programming (TFP), 2023.
Specification-based Symbolic Execution for Stateful Network Protocol Implementations in the IoT.
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IEEE Internet of Things Journal (IoT-J), 2023.
SISL: Concolic Testing of Structured Binary Input Formats via Partial Specification.
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International Symposium on Automated Technology for Verification and Analysis (ATVA), 2022.
3D Visualization of Symbolic Execution Traces.
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Forum for Specification and Design Languages (FDL), 2022.
Towards Quantification and Visualization of the Effects of Concretization during Concolic Testing.
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IEEE Embedded Systems Letters (ESL), 2022.
SymEx-VP: An open source virtual prototype for OS-agnostic concolic testing of IoT firmware.
DOI
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Journal of Systems Architecture (JSA), 2022.
Automated Detection of Spatial Memory Safety Violations for Constrained Devices.
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27th Asia and South Pacific Design Automation Conference (ASP-DAC), 2022.
In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes.
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Forum for Specification and Design Languages (FDL), 2021.
Adaptive simulation with Virtual Prototypes in an open-source RISC-V evaluation platform.
DOI
Journal of Systems Architecture (JSA), 2021.
Towards Reliable Spatial Memory Safety for Embedded Software by Combining Checked C with Concolic Testing.
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58th ACM/IEEE Design Automation Conference (DAC), 2021.
An Effective Methodology for Integrating Concolic Testing with SystemC-based Virtual Prototypes.
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Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021.
Mutation-based Compliance Testing for RISC-V.
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26th Asia and South Pacific Design Automation Conference (ASP-DAC), 2021.
Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime.
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Video
IEEE 38th International Conference on Computer Design (ICCD), 2020.